Conventional memory block architectures implement memory cells arranged in rows and columns to form one or more arrays. Furthermore, the columns of the array are divided into groups of columns. A particular cell of the memory block is written to or read from by selecting the appropriate (i) row, (ii) group and (iii) column within the group. Conventional memory arrays use redundant memory cells and wordlines to compensate for production errors.
The redundant memory cells are also arranged in rows (e.g., redundant rows) and columns (e.g., redundant columns) to form arrays. After the production of a complete memory array, a post production test of the memory array is generally performed. If the post-production testing indicates that one or more cells of the memory array are defective, redundant memory cells can be substituted.
The substitution typically occurs after the entire memory array has been manufactured. If one or more cells in a row are defective, the entire row is replaced by a redundant row. Similarly, if one or more cells in a column are defective, then the entire column is replaced by a redundant column. Replacement of a defective cell by a single redundant cell is not common, because of high overhead associated with such a scheme. By allowing the defective memory cells to be replaced by the redundant cells after production, the memory array can still be used. Conventional approaches to disable a faulty row or column use one or more fuses to disable the faulty portion(s). It is desirable to provide a method and/or architecture for row redundancy that may not require additional disable fuses.
Referring to FIG. 1, a circuit 100 is shown implementing a conventional row redundancy scheme. The circuit 100 generally comprises a row decoder 102, a word line driver 104, a memory array 106, a redundant row programming logic 108, a word line driver 110, a group decoder 112 and a fuse block 114. The word line driver 104 is implemented to select a regular row. The word line driver 110 is implemented to select a redundant row. The group decoder 112 is implemented to select a group of the memory array 106. The fuse block 114 is configured to disable faulty rows of the memory array 106. Each regular row has a disable fuse (e.g., fuse block 114). If the memory array 106 comprises `n` rows, then `n` disable fuses are required (where n is an integer). If a particular row is faulty, the respective disable fuse is blown using a laser (not shown). The disabled fuse prevents the faulty row from being written to and/or read from. The fuse block 114 consumes a large amount of die area. For example, a single Meg SRAM 106 has 1000 disabling fuses if the memory cells are arrayed into 1000 rows and 1000 columns. In another example, a single Meg SRAM 106 has 2000 disabling fuses if the memory cells are arrayed into 2000 rows and 500 columns. The conventional approach of FIG. 1 consumes a large amount of die area for the disabling fuses (fuse block 114), even if no redundancy is required.